January JEDEC. STANDARD. DDR2 SDRAM SPECIFICATION be addressed to JEDEC Solid State Technology Association, Wilson Boulevard. DDR2 SDRAM is a double data rate synchronous dynamic random-access memory interface. It superseded the original DDR SDRAM specification, and is superseded by .. JEDEC standard: DDR2 SDRAM Specification: JESDF, November ** ยท JEDEC. The JEDEC memory standards are the specifications for semiconductor memory circuits and Memory modules of the DDR2-SDRAM type are available for laptop, desktop, and server computers in a wide selection of capacities and access.

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The specification contains definitions of the commonly used prefixes kilomegaand giga usually combined with the units byte and bit to designate multiples of the units. The standards specify memory module label formats for end-user markets. Bandwidth is calculated by taking transfers per second and multiplying by eight.

DDR2 started to become competitive against the older DDR standard by the end ofas modules with lower latencies became available.

The standards specify the physical and electrical characteristics of the modules, and include the data for computer simulations of the memory module operating in a system. The document further refers to the description of the IEC binary prefixes in Amendment 2 of IEC”Letter symbols to be used in electrical technology”for an alternate system of prefixes [notes 1] and includes a table of the IEC prefixes in the note.

This committee consists of members from manufacturers of microprocessors, memory ICs, memory modules, and other components, as well as component integrators, such as video card and personal computer makers.

  ISO 14726 1 PDF

It had severe overheating issues due to the nominal DDR voltages. During an access, four bits were read or written to or from a four-bit-deep prefetch queue.

JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. The documentation of modern memory modules, such as the standards for the memory ICs [4] and a reference design of the module [5] requires over one hundred pages.

An alternative system is found in Amendment 2 to IEC This packaging change was necessary to maintain signal integrity at higher bus speeds. DDR2 was introduced in the second quarter of at two initial clock rates: From Wikipedia, the free encyclopedia.

JEDEC memory standards

The document notes that these prefixes are used in their decimal sense for serial communication data rates measured in bits. Retrieved August 25, This is because DDR2 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.

Alternatively, DDR2 memory operating at twice the external data bus clock rate as DDR may provide twice the bandwidth with the same latency. This page was last edited on 2 Augustat Retrieved from ” https: Power savings are achieved primarily specifiaction to an improved manufacturing process through die shrinkage, resulting in a ddd2 in operating voltage 1.


Wikipedia articles in need of updating from January All Wikipedia articles in need of updating. These chips are mostly standard DDR chips that have been tested and rated to be capable of operation at higher clock rates by the manufacturer. By using this site, you agree to the Terms of Use and Privacy Policy. Please specifictaion this article to reflect recent events or newly available information.


Both performed worse than the original DDR specification due to higher latency, which made total access times longer. From Wikipedia, the free encyclopedia. In addition to double pumping the data bus as in DDR SDRAM transferring data on the rising and falling edges of the bus clock specificatioDDR2 allows higher bus speed and requires lower power by running the internal clock at half the speed of the data bus.

Archived from the original on This queue received or transmitted its data over the data bus in two data bus clock cycles each clock cycle transferred two bits of data.

JEDEC memory standards – Wikipedia

In other projects Wikimedia Commons. Such chips draw significantly more power than slower-clocked chips, but usually offered little or no improvement in real-world performance.

Retrieved from ” https: DIMMs are identified by their peak transfer capacity often called bandwidth. However, latency is greatly increased as a trade-off. DDR2’s bus frequency is boosted by electrical interface improvements, on-die terminationprefetch buffers and off-chip drivers. The specificarion of kilo, giga, and mega based on powers of two are included only to reflect common usage. Views Read Edit View history.